1. Field of the Invention
The present invention relates to a semiconductor device including a high withstand-voltage MOS transistor and method of fabricating the same.
2. Description of the Related Art
As a high potential of 10 V, 100 V or so is applied to the output stage of a semiconductor device which drives an LCD (Liquid Crystal Display) or a PDP (Plasma Display Panel), an attempt is made to increase the withstand voltage of an MOS transistor that constitutes the output stage. FIG. 1 shows one example of a conventional high withstand-voltage MOS transistor which is used for such a purpose (Japanese Patent Laid-Open Publication No. H11-163336/1999). An N channel MOS transistor is formed in a device forming region defined by a thick insulating layer (LOCOS layer) 202 formed in a P-type semiconductor substrate 201 of silicon. The MOS transistor has a gate oxide layer 203 and a gate electrode 204 formed at the surface of the semiconductor substrate, and a high-concentration N-type drain diffusion layer 205 and a high-concentration N-type source diffusion layer 206 formed on the respective sides of the gate electrode 204. In the MOS transistor, in order to improve the drain withstand voltage, an LOCOS layer 202a as a thick gate insulating layer is formed at the surface of the substrate in a part of the channel region between the gate electrode 204 and the drain diffusion layer 205, and a low-concentration P-type field relaxing diffusion layer 207 is formed in a region including the drain diffusion layer 205 and a part of the channel region. In FIG. 1, “231” denotes an intermediate insulating layer, “232” denotes a contact plug and “233” denotes a first wire layer.
In the high withstand-voltage MOS transistor, the thick gate insulating layer comprised of the LOCOS layer 202 can ensure a longer electric length between the gate electrode 204 and the drain diffusion layer 205 and the field relaxing diffusion layer 207 can restrain the spreading of the depletion layer that is generated when a potential is applied to the drain diffusion layer 205. This makes it possible to relax field concentration at the drain junction or the junction between the field relaxing diffusion layer 207 and the semiconductor substrate 201 and prevents the current leak from occurring due to breakdown of the electric field, thereby improving the drain withstand voltage. Japanese Patent Laid-Open Publication No. H11-163336/1999 also describes a technique of forming a diffusion layer with an intermediate concentration for relaxing the electric field in the field relaxing diffusion layer in order to further improve the withstand voltage.
However, the present inventor has found out that even in such an MOS transistor having the field relaxing diffusion layer 207, when a high potential needed to drive an LCD or PDP is supplied to the drain, field concentration occurs at the surface portion of the semiconductor substrate at the boundary between the field relaxing diffusion layer 207 and the channel region and makes it difficult to achieve the required high withstand voltage. To improve the withstand voltage and achieve the required high withstand voltage in the MOS transistor, for example, the length of the LOCOS layer 202a may be increased to make the electric length between the gate electrode 204 and the drain diffusion layer 205 longer or the field relaxing diffusion layer 207 may be stretched toward the channel region, thereby weakening the electric field at the field relaxing diffusion layer 207. This scheme however increases the sizes of the drain diffusion layer 205 and the channel region, thereby making the size of the MOS transistor larger, which stands in the way of higher integration of semiconductor devices.
A bidirectional MOS transistor has also been proposed which has an field relaxing diffusion layer formed on both the drain diffusion layer and the source diffusion layer and has a thick gate insulating layer also formed not only on the drain diffusion layer but also between the source diffusion layer and the gate electrode. In such a bidirectional MOS transistor, enlarging the field relaxing diffusion layers on both the source and drain sides or making the thick gate insulating layer longer to increase the withstand voltage makes the device size larger.